As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. Thus, VFETs are an attractive option for technology scaling for 5 nanometer (nm) and beyond.
Floating gate memory cells, which form the basis of flash memory, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM) and electrically-erasable programmable read-only memory (EEPROM). Floating gate memory cells are important to the implementation of any technology.
Therefore, techniques for co-integration of non-volatile memories in a vertical FET technology would be desirable.